The Granularity of Soft-Error Containment in Shared Memory Multiprocessors

Enables flexibility in when to detect Case Study: HP NSAA HP’s NonStop Advanced Architecture (NSAA), although not a shared-memory multiprocessor, uses the memory containment granularity. Before performing disk or network I/O, NSAA compares redundant executions. Recovery is accomplished by reverting to a software-created backup process. Recovery Across I/O When coordinating checkpoints across all processors, a major challenge becomes the apparent need to recover across I/O. Nakano et al. observe that some common I/O operations are idempotent, which permits coordinated checkpoints for I/O intensive workloads (e.g., TPC-C or HTTP servers). Case Study: TRUSS The TRUSS server architecture provides a logical separation layer (Membrane) that enables processor cores and caches to locally checkpoint and recover, independent of other processors or memory. Each processor core and cache form a containment boundary such that all shared-memory interactions are guaranteed error-free. With hardware support for checkpointing and error detection, the TRUSS architecture provides software-transparent reliability for soft errors and a broad class of permanent faults. Other Examples: HP NonStop, Stratus, etc. Case Study: IBM z-series The IBM z-series mainframe uses a custom processor core that consists of two lockstepped, replicated pipelines. Before retiring an instruction, the results from both executions are compared, and if an error is detected, the instruction is re-executed. Case Study: Redundant Multithreading Recent work suggests that time-delayed redundant execution using SMT or CMP architectures can improve resource efficiency over lockstepped DMR. In these proposals, error detection is enforced either before the register file or before the cache. Both satisfy the core containment granularity. Soft-error rates (SER) increasing exponentially What are the key sources? Radiation: SER scales with transistor count Variability: SER increases with level of integration – Manufacturing: device variations within/across dies – Lifetime: transistor performance varies over time